Turning to FIG. 1, an example of a conventional PLL 100 can be seen. In operation, the phase/frequency detector (PFD) 102 generates up and down control signal for the charge pump 104 in response to the phase error between the reference signal REF and feedback signal FB from divider 110. The charge pump 104 then applies the appropriate current (charge) to the low pass filter (LPF) 106 (which is generally comprised of capacitors C1 and C2 and resistor R1). The LPF 106 then provides a voltage to the control node of voltage controlled oscillator (VCO) 108 (which is an all-CMOS VCO). Because VCO 108 is an all-CMOS VCO, PLL 100 suffers from excessive phase noise and jitter caused by the LPF 106. This is largely due to very high VCO gain (KVCO) of CMOS oscillators (within VCO 108), which effectively multiplies the noise from the filter resistor R1 modulating the control node of the VCO 108. Thus, the noise from LPF 106 is the dominant noise source, limiting the performance.
Therefore, there is a need for an improved PLL.
Some examples of conventional circuits are: U.S. Pat. Nos. 7,167,056; 7,298,221; and U.S. patent application Ser. No. 12/726,190.